By default, the Vivado IDE compiles .v files with the Verilog 2001 syntax and .sv files with
the SystemVerilog syntax

See Also

• ug900 vivado logic simulation
• ug937 vivado simulation tutorial

ACP: Accelerator Coherency Port

Interface enabling coherent accesses from PL to CPU memory space

Zynq 7000

Zynq UltraScale+ MPSoC

One 64-bit AXI slave interface (ACP port) for coherent access to CPU memory

The two highest performance interfaces between the PS and the PL for data transfer are the high-performance AXI ports and ACP interfaces. The high performance AXI ports are used for high throughput data transfer between the PS and the PL.Coherency, if required, is managed under software control. When hardware cohere...

Listing the JTAG chain through XSDB can help identify hardware connectivity issues. To perform this operation you use the "jtag targets" command. Below is a sample session on how to perform this operation on the first cable detected.

connect -host <ip-or-hostname>
jtag targets -set -filter {level == 0}
jtag targets -filter {level == 1}

get_parts

The command get_parts returns a list of matching parts.

Example:

    set mypart "xc7k325t"
    set device_filter [format "%s*" $mypart]
    foreach part_pkg [get_parts -filter "DEVICE =~ $device_filter" ] {
        set pin_count [get_property IO_PIN_COUNT $part_pkg]
        set row_data [format "INFO: part %s, pins %s" $part_pkg $pin_count]
        puts $row_data    
    }