ACP: Accelerator Coherency Port
Interface enabling coherent accesses from PL to CPU memory space
Zynq 7000
Zynq UltraScale+ MPSoC
One 64-bit AXI slave interface (ACP port) for coherent access to CPU memory
The two highest performance interfaces between the PS and the PL for data transfer are the high-performance AXI ports and ACP interfaces. The high performance AXI ports are used for high throughput data transfer between the PS and the PL.Coherency, if required, is managed under software control. When hardware coherent access to the CPU memory is required, the ACP port is to be used.
The accelerator coherency port (ACP) is a 64-bit AXI slave interface that provides connectivity between the APU and a potential accelerator function in the PL. The ACP directly connects the PL to the snoop control unit (SCU) of the ARM Cortex-A9 processors, enabling cache-coherent access to CPU data in the L1 and L2 caches. The ACP provides a low latency path between the PS and a PL-based accelerator when compared with a legacy cache flushing and loading scheme.
